1. Technical Field
The present invention relates to a system and method for advanced logic built-in self test (LBIST) with selection of scan channels. More particularly, the present invention relates to a system and method for loading a device's scan chains through sequential or interleaved loading techniques in order to minimize instantaneous power requirements during an LBIST.
2. Description of the Related Art
Devices have used logic built-in self test (LBIST) for years in order to determine the device circuitry's integrity. To perform an LBIST, an LBIST controller loads scan patterns into scan chains and initiates one or more functional cycles, which, in turn, propagates the scan pattern values throughout the device's circuitry. Responses are then captured and logged into a multiple-input signature register (MISR). Each LBIST controller may drive a number of scan chains depending upon the number of channels the LBIST controller supports.
A challenge found during an LBIST controller's load/scan phase is that a substantial amount of latches clock simultaneously, which draws a tremendous amount of current from a device's power supply. This large current demand creates a change in current per unit time (di/dt) many times larger than what a device typically experiences during functional operation.
Existing art attempts to alleviate the LBIST controller's large di/dt demand by inserting hold or idle cycles between load/scan cycles. Meaning, if an LBIST controller supports four scan channels, the LBIST controller loads a scan bit into all four scan channels during a single clock cycle, and then waits a number of clock cycles before loading more scan bits. A challenge found with this approach, however, is that a tremendous amount of current is still required during clock cycles that the LBIST controller loads scan bits.
What is needed, therefore, is a system and method that minimizes instantaneous power requirements during an LBIST.